As electronic devices and apparatus using such devices become more and more complicated and/or "user-friendly", they require larger and larger amounts of memory in order to store the software necessary for them to function as desired. Accordingly, either the number of blocks of ROM on a particular chip need to increase, which increases the chip cost and size thereby reducing the manufacturing yield, or extra memory chips must be provided in the apparatus.
There is therefore a need for memory arrays which have a structure allowing the memory cells, formed of individual MOS transistors, to be arranged as densely as possible in the array, so as to increase the data storage capacity of a given area on a semiconductor chip.
A number of solutions to try to increase the cell density of ROM have been proposed. In European Patent Application EP 0109853, published May 30, 1985, there is described an array of MOS transistors formed in a semiconductor substrate having a plurality of continuous diffused lines (bit lines), with alternate diffused lines serving, respectively, as the source and drain regions of a number of the MOS transistors. A plurality of conductive word lines are formed over, and insulated from, the diffused lines, crossing the diffused lines at right angles, with each conductive word line serving as the gates of a number of MOS transistors. Each transistor of the memory array is thus formed in a region having two continuous diffused lines and a single word line, with a single electrical contact to a bit line being formed for each such diffused line.
In order to reduce the capacitance between the diffused lines and the conductive (polycrystalline silicon) line, a thin layer of field oxide is produced over the diffused lines to isolate the diffused lines from the polycrystalline line. Furthermore, a thick layer of field oxide is generally required in the region between adjacent diffused lines and adjacent polycrystalline lines in order to isolate one memory cell from adjacent cells in order to minimize electric coupling between them.
The memory array is programmed by causing the threshold voltage of particular transistors to be increased, with respect to the other transistors, so that when a voltage is placed on the transistor's gate, a transistor with a lower threshold voltage will turn on, and thus conduct between its drain and source regions, indicating a logical "1", whereas a transistor with a higher threshold voltage will not conduct, indicating a logical "0". This programming is achieved by implanting the region of silicon between the diffused lines forming the source and drain regions of a selected transistor and below the polycrystalline line forming the gate of the selected transistor with an implant, for example of boron ions, to produce the required threshold voltage.
In U.S. Pat. No. 5,449,633, published on Sep. 12 1995, there is disclosed an alternate metal virtual ground (AMG) ROM array formed in a silicon substrate of P-type silicon. The array includes a ROM cell matrix which is defined by a plurality of rows and a plurality of columns of ROM data storage cells. The AMG ROM array includes a plurality of parallel, spaced-apart buried N+ bit lines formed in the silicon substrate. Alternate buried N+ bit lines are contacted by a conductive metal line at two contact locations within an array segment to thereby define contacted drain bit lines of the ROM cell matrix. Each buried N+ bit line that is between adjacent contacted drain bit lines is not contacted. Each non-contacted bit line is segmented into a length sufficient to form the segmented source bit line for a preselected plurality, for example 32 or 64, of ROM data storage cells, thereby defining a column of the ROM data storage cells in the ROM segment. That is, a first column of ROM data storage cells is connected between the segmented source bit line and the first adjacent contacted drain bit line. A second column of ROM data storage cells is connected between the segmented source line and the second adjacent contacted drain bit line. Each ROM segment thus consists of 32 or 64 cells, with each segment being isolated from each adjacent segment by field oxide regions and a segment select line is provided to select which particular ROM segment is to be read. The cells are programmed by implanting with boron ions, as described above, before the polycrystalline conducting line is formed over the N+ bit lines.
In each of the above two cases, therefore, large amounts of field oxide isolation are required to produce the ROM block. Such areas of field oxide isolation are undesirable because the process of growing field oxide layers causes the field oxide to eat into the active areas thereby reducing their size. In order to prevent this, the active areas must have a minimum spacing, thereby limiting increases in density.
In the first array described above, having one electrical metal contact line connected to each bit line means that there must be a relatively high density of metal lines on the chip, because and increasing the cell density would increase the density of the metal lines, which is very difficult to manufacture because the required masking and etching steps would need to produce very fine lines.
Furthermore, in the second array described above, the step of programming the cells takes place early on in the fabrication process, so that, for each different programming required, a relatively large amount of manufacturing must still be carried out after the programming is known and therefore the time taken to produce the finished product after the programming is known is still relatively high.
Thus, in order to produce denser ROM arrays, it would be desirable to reduce the number of metal contact lines required to read the data cells and to reduce the amount of field oxide required.